1. Field of the Invention
The present invention relates to an image processing apparatus and, more particularly, to compression encoding processing for image signals.
2. Related Background Art
As an apparatus for recording and reproducing image signals, a VTR based on a high-efficiency encoding method has been proposed. In this apparatus, the pixels of a frame are digitized and grouped into blocks each consisting of a predetermined number of pixels, and entropy coding is then performed by orthogonal transformation (e.g., discrete cosine transform (DCT)) and quantization.
As one of such conventional techniques, a home digital VTR format has been proposed. In this technique, an existing television signal is digitized, and the resultant information is recorded after it is compressed to about 1/6.
FIG. 17 is a block diagram showing the arrangement of a VTR with a built-in camera as one of the proposed home digital VTRs.
Referring to FIG. 17, the VTR includes a lens group 1, an image pickup element 2 such as a CCD, a camera signal processing circuit 3 for converting a signal from the image pickup element 2 into a television signal, an LCD display circuit 4 for displaying a photographed image on an LCD (liquid crystal display) monitor, an LCD monitor 5 used as a finder, and a block dividing and shuffling circuit 6 for dividing a television signal corresponding to one frame into a plurality of blocks, and shuffling the blocks.
A motion detection circuit 7 detects whether a picture exhibits a larger or small motion (the correlation between frames is larger or small). A DCT calculation weighting circuit 8 performs a weighting operation in accordance with DCT calculation and a spatial frequency component. A sort circuit 9 sorts DCT coefficients, which are obtained by the DCT calculation weighting circuit 8 upon orthogonal transformation, in the order of increasing frequencies.
A code amount estimation circuit 10 obtains a quantization step width with which a code amount obtained by quantization of data of a predetermined number of blocks and variable length encoding is made constant. An adaptive quantization circuit 11 performs quantization upon reception of the estimation result from the code amount estimation circuit 10. A variable length encoding circuit 12 performs variable length encoding by using two-dimensional Huffman codes. A deshuffling circuit 13 deshuffles data to their original positions on a frame obtained before data compression. A recording processing circuit 14 adds signals required for a recording operation, e.g., an error correction code, sync signals, and a pilot signal. The apparatus also includes a magnetic head 15 and a magnetic tape 16.
The operation of the digital VTR with the built-in camera having the above arrangement will be described below.
First of all, an object image is formed on the image pickup element 2 such as a CCD through the lens group 1, and converted into an electrical signal.
The electrical signal from the image pickup element 2 is subjected to .gamma. correction, color matrix processing, and the like in the camera signal processing circuit 3 to form a television signal.
A general VTR with a built-in camera (camcorder) allows an operator to monitor a photographed image through the finder. An output from the camera signal processing circuit 3 is converted into an LCD driving signal by the LCD display circuit 4 to display an image on the LCD monitor 5.
The output from the camera signal processing circuit 3 is also sent to a recording system. The block dividing and shuffling circuit 6 divides and shuffles blocks.
The output from the camera signal processing circuit 3 may be analog or digital data. If the output is analog data, an A/D converter is to be connected to the input side of the block dividing and shuffling circuit 6.
A method of dividing and shuffling blocks will be described below with reference to FIGS. 2 and 3.
First of all, signals corresponding to one frame, i.e., a luminance (Y) signal and color difference (R-Y and B-Y) signals, are divided into DCT blocks each consisting of (8.times.8) pixels.
Subsequently, as shown in FIG. 2, four Y signal blocks, one R-Y signal block, and one B-Y signal block, i.e., a total of six DCT blocks, which are located at the same position on the frame are grouped into a macro block as a unit.
As shown in FIG. 3, one frame is divided into five areas A to E, and each area is divided into 10 blocks each consisting of 27 macro blocks.
That is, one frame is divided into five areas in the horizontal direction and 10 areas in the vertical direction. Each of these divided blocks is called a super-block.
Shuffling is performed in units of macro blocks. In the subsequent circuits, one macro block is selected from each of the five areas A to E according to a predetermined rule, and processing is performed such that the image data of the five macro blocks collected from the respective areas becomes fixed length data after data compression.
The DCT calculation weighting circuit 8 performs DCT calculation in units of DCT blocks, and performs a weighting operation such that a component having a low spatial frequency exhibits a smaller distortion than a component having a high spatial frequency.
The DCT calculation weighting circuit 8 performs intrafield processing when a picture exhibits a large motion, and performs intraframe processing when a picture exhibits a large motion. The motion detection circuit 7 determines processing to be performed by the DCT calculation weighting circuit 8.
The sort circuit 9 sorts DCT coefficients, which are obtained by the DCT calculation weighting circuit 8 upon orthogonal transformation, in the order of increasing frequencies. A quantization step width for the sorted image data is determined in the adaptive quantization circuit 11 in accordance with the frequency of an AC component. As described above, control is performed such that the data of the five macro blocks becomes fixed length data after compression. This control is performed by the code amount estimation circuit 10. The code amount estimation circuit 10 sets a parameter in accordance with the characteristics of an image corresponding to each DCT block, and obtains an quantization step width corresponding to the parameter and a frequency component, thereby realizing fixed length conversion with efficient bit allocation to each DCT block.
Although the image data quantized by the adaptive quantization circuit 11 is encoded into variable length codes by the variable length encoding circuit 12, the five macro blocks are almost kept to be fixed length data.
The deshuffling circuit 13 deshuffles the image data compressed by the deshuffling circuit 13 to the original positions on the frame. By deshuffling the data to the original positions on the frame, a picture in the fast playback mode is made more legible.
The recording processing circuit 14 adds signals required for a recording operation, e.g., an error correction code, sync signals, and a pilot signal, to the deshuffled image data. The resultant data is recorded on the magnetic tape 16 by the magnetic head 15.
The above prior art is very effective when the entire frame of a picture is uniformly compressed. In general, however, a photographer tends to fix his/her eye on only an object to be photographed in a frame. In addition, when there are a plurality of objects at different distances, since only one target object is in focus, it is highly possible that the remaining objects are out of focus.
In spite of such a situation, however, according to the above prior art, since bits are uniformly allocated to the entire frame, many bits are used for even unnecessary portions.